A common type of semiconductor memory device is the random access memory (RAM). RAMs include many data storage locations each having a particular address. To read data from the RAM, an address is applied to the RAM in conjunction with a read command and stored data is provided at input/output (I/O) pins. To write data into a RAM, an address is applied to the RAM in conjunction with a write command, and at the same time, data is applied to the I/O pins. The applied data is then stored at the location corresponding to the applied address. The process of selecting a storage location in response to an applied address, is referred to as decoding, and the various bits of the applied address must be decoded by logic circuits to arrive at the correct data location.
Among the many important performance features of a RAM device is the amount of power the device consumes. Reduction in RAM power consumption has been a consistent and important goal in RAM design. Power consumption can be a critical aspect of device performance in portable applications having finite power supplies, such as re-chargeable batteries. Thus, any modifications to RAMs that can reduce power consumption are valuable advances in the art. This is reflected by the fact that RAMs having lower power requirements can often command higher prices in the marketplace.
While low power consumption is desirable, the physical size of a RAM is also a very important feature in a RAM design. Because RAMs are typically semiconductor devices manufactured on semiconductor wafers, the smaller the size of the RAM, the larger the number of devices which can be fit on the wafer. Thus, a smaller device size allows more products to be created with same starting material, this can reduce the overall manufacturing cost of a RAM. Conversely, larger RAM sizes are less cost effective. The size of semiconductor memory devices is usually discussed in terms of its "die" size. Thus, any RAM features which results in increases in the die size of a RAM are undesirable.
A common circuit element in a semiconductor RAM is the sense amplifier. Sense amplifiers "sense" the logic stored within a memory cell by amplifying the relatively small data signals provided by the memory cells. Some RAM devices, dynamic RAMs (DRAMs) in particular, also use sense amplifiers to refresh memory cell data. Thus, in a read operation of a DRAM, even though entire banks of sense amplifiers are activated, output data will be read from only a portion of the activated sense amplifiers. The number of sense amplifier banks that are activated by a RAM in a read operation is sometimes referred to as the "page" size of RAM. It follows that RAMs having large page sizes will consume more power, as they will activate a larger number of sense amplifiers.
The overall functional arrangement of a RAM is often described in terms of the RAM's architecture. The RAM architecture often includes those functional elements required for reading data from, and writing data into the RAM. The physical depiction of a RAM architecture can often mimic the actual physical appearance of the manufactured semiconductor device, because circuit blocks and conductive lines are drawn in the same relationship to one another, as they will physically appear on the manufactured device.
Referring now to FIG. 1, a block diagram is set forth generally illustrating a random access memory (RAM) architecture of the prior art. The RAM is a 64-megabit RAM having a 128-bit I/O space. The RAM is designated by the general reference character 100 and represents a RAM having a large page size. The RAM 100 is shown to include a number of array blocks, each designated by the general reference character 102. Each array block is further identified by two numbers contained within parentheses, which generally identify the array bank's position within the RAM 100. The first number represents a bank, the second number represents a quadrant. Thus, array block 102(0,0) is in bank number zero and quadrant number zero.
The RAM 100 of FIG. 1 is shown to include sixteen banks, shown as 104(0) to 104(15), each including four array blocks 102. In addition, the RAM 100 can be further conceptualized as being divided into four quadrants. Each quadrant includes one quarter of the array banks, when viewed in the column direction. Thus, array blocks 102(0,0), 102(1,0), 102(2,0) . . . 102(15,0) form the first quadrant, shown as 106a. The remaining three quadrants are shown as 106b to 106d. Each array block (102(0,0)-102(15,3)) includes memory cells that are accessed by row decoder blocks and column decoder blocks. In the architecture of FIG. 1, a first block of row decoders 108a are shown to be coupled to the first quadrant 106a and the second quadrant 106b, and a second block of row decoders 108b is shown coupled to the third quadrant 1106c and the fourth quadrant 106d. The RAM 100 further includes four column decoder blocks, 110a to 110d, each associated with one quadrant 106a to 106d.
Two array blocks (102(0,0) and 102(1,0)) from the architecture of FIG. 1 are set forth in more detail in FIG. 2. Each array block (102(0,0) and 102(1,0)) includes the same general elements. Accordingly, like elements will be referred to by the same reference character, with the elements of array block 102(0,0) ending with the letter "a," and the elements of array block 102(1,0) ending with the letter "b." Each array block 102(0,0) and 102(1,0) includes a memory cell array (200a, 200b), a top bank of sense amplifiers (202a and 202b), a bottom bank of sense amplifiers (204a and 204b), a top Y-select circuit (206a and 206b), and a bottom Y-select circuit (208a and 208b). It is noted that the bottom Y-select circuit 208a of array bank 102(0,0) is the same as the top Y-select circuit 206a of array bank 102(1,0).
The memory cell arrays (200a, 200b) each have a 1 megabit (1 Mb), or 1,048,576 bit storage capacity. Thus, each memory cell array includes 1,048,576 memory cells. The memory cells are accessed by 2048 (2 k) pairs of bit lines and 512 word lines. The top bank of sense amplifiers (202a and 202b) includes 1024 ("1 k") sense amplifiers for amplifying data signals on half of the bit line pairs in its respective memory array. The bottom bank of sense amplifiers (204a and 204b) also includes 1 k sense amplifiers, and amplifies data signals on the other half of bit lines in its respective memory array. The top Y-select circuits (206a and 206b) and bottom Y-select circuits (208a and 208b) receive Y-select signals from the column decoder 110a, and in response thereto, couple selected bit lines to I/O lines.
The I/O line arrangement for array blocks (102(0,0) and 102(1,0)) is set forth in FIG. 3. FIG. 3 illustrates essentially one eighth of memory quadrant 106a. When viewed with respect to the I/O lines, each array block is logically divided into eight array sections, shown as 300(i,j), where i represents the bank in which the array section is located, and j represents the position of the array section within the array block (102(0,0) and 102(1,0)). In the architecture of FIGS. 1-3, each array block (102(0,0) and 102(1,0)) is divided into eight array sections. Therefore, each array section (300(0,0) to 300(1,7)) includes 256 bit line pairs. coupled to 128 sense amplifiers of a top bank (202a and 202b) and 128 sense amplifiers of a bottom bank (204a and 204b). In addition, each array section (300(0,0) to 300(1,7)) includes a portion of the top Y-select circuits (206a and 206b) and bottom Y-select circuits (208a and 208b).
The I/O line arrangement is shown in FIG. 3 includes two top local I/O (LIO) line pairs, and two bottom local I/O line pairs associated with each array section (300(0,0) to 300(1,7)). The top LIO pairs are designated by the reference characters 302(i,j) and the bottom LIO pairs are designated by the reference characters 304(i,j). For example, array section 300(0,0) has an associated two top LIO pairs 302(0,0) and an associated two bottom LIO line pairs 304(0,0). In a similar manner to the Y-select circuits in FIG. 2, the bottom LIO line pairs for one array section serve as the top LIO line pairs for the array section below. For example, the bottom LIO lines 304(0,0) for array section 300(0,0) are the same as the top LIO lines 302(1,0) for array section 300(1,0).
The LIO lines are coupled to global I/O lines (GIO) by I/O select blocks. The I/O select blocks include a top I/O select block 306(i,j) and bottom I/O select block 308(i,j). As in the case of the top and bottom LIO lines, the bottom I/O select blocks (308(0,0) to 308(0,7)) for the array block 102(0,0), serve as the top I/O select blocks (306(1,0) to 306(1,7)) for the array block 102(1,0). The GIO lines are grouped into pairs, and are shown as items 310(0) to 310(31). The I/O select blocks of a given array block are activated at the same time as the sense amplifier banks of that array block. For example, in the case of FIG. 3, when the sense amplifiers of array block 102(0,0) are enabled, upper I/O blocks 306(0,0) to 306(0,7) and lower I/O blocks 308(0,0) to 308(0,7) are also enabled. In contrast, when the sense amplifiers of array block 102(1,0) are enabled, upper I/O blocks 306(1,0) to 306(1,7) (which are the same as lower I/O blocks 308(0,0) to 308(0,7)) and lower I/O blocks 308(1,0) to 308(1,7) are enabled.
The same general I/O configuration set forth in FIG. 3 is repeated throughout the RAM 100 shown in FIG. 1, resulting in 32 GIO pairs being provided per quadrant, for a total I/O space of 128 bits.
Data locations within the RAM 100 are accessed via the GIO pairs, by selecting one of the banks (104(0) to 104(15)), and applying a column address and a row address. In this manner, the bank select information, column address, and row address are decoded by the RAM 100 to access one of the 512k 128-bit locations within the RAM 100. The decoding arrangement of the RAM 100 is illustrated in FIGS. 4a and 4b. FIG. 4a is a table setting forth the bank select decoding scheme and row decoding scheme. The RAM 100 receives bank select decode information in the form of four bank select bits, shown as BA0-BA3. A bank (104(0) to 104(15)) is selected according to the various combinations of the possible BA0-BA3 values. The BA0-BA3 values may be derived from a portion of an applied address. The 512 rows within each bank (104(0) to 104(15)), are selected by a row address which includes row address bits RA0-RA8. Thus, the application of bank select information (BA0-BA3) and row address information (RA0-RA8) results in the selection of one of the word lines within the RAM 100.
The selection of columns within the RAM 100 is illustrated in FIG. 4b. FIG. 4b sets forth the column selection arrangement for one quadrant 106a of the RAM 100. The 2k columns of the quadrant 106a are logically divided into eight groups of 256 columns each. Four columns are selected from the 256 of each group by the application of column address bits, shown as CA0-CA5. In response to the application of the CA0-CA5 values, one Y-select signal within each 256 column group will be activated, and select four columns to place data on four local I/Os. In this manner, the application of the column address information (CA0-CA5) selects 32 columns in each quadrant (106a-106d) to provide the 128 bit I/O space.
If reference is made to FIG. 4b in conjunction with FIG. 3, it is noted that the application of each particular CA0-CA5 combination, results in the activation of one of sixty-four Y-select signals coupled to each array section (300(0,0) to 300(1,7)). In response to each different Y-select signal, the portions of the upper and lower Y-select circuits within each array section (300(0,0) to 300(1,7)) couple data to the upper and lower LIO lines (302 and 304) of the array section. In other words, each Y-select signal, selects four data bits from an array section.
Referring back to FIG. 1, it is noted that array blocks 102(0,0) to 102(0,3) are hatched. This indicates that the sense amplifiers within the array blocks (102(0,0) to 102(0,3)) are active. The RAM 100 is considered to be a "large" page size RAM because, in a read operation, the sense amplifier banks for all the array blocks within a bank are activated at the same time.
As previously noted, the activation of sense amplifiers can consume considerable power in a RAM 100. One approach to reducing the amount of power consumed by a RAM is to decrease the page size of the RAM. This reduces the number of sense amplifiers that are active in a read cycle. FIG. 5 illustrates one example of a reduced page size RAM approach. Unlike the RAM of FIG. 1, which is logically divided into 512 rows and 64 columns per bank, the architecture of FIG. 5 illustrates a RAM that is logically divided into 1k rows and 32 columns per bank. The reduced page size RAM is designated by the general reference character 500 and includes many of the same elements as the RAM 100 of FIG. 1. To that extent, like elements will be referred to by the same reference character, except that the elements of FIG. 5 will begin with the number "5" instead of the number "1."
The reduced page size RAM 500 has the same general configuration as the RAM 100 of FIG. 1, including array blocks (502(0,0) to 502(15,3)) arranged into sixteen banks (504(0) to 504(15)) and four quadrants (506a to 506d). In addition, two row decoder blocks (508a and 508b) are situated between the quadrants (506a-506d), and a column decoder block (510a-510d) is associated with each quadrant (506a-506d).
The decoding arrangement of the reduced page size RAM 500 is similar to that of the RAM 100 set forth in FIG. 1. Bank select information results in the selection of one of the banks (504(0) to 504(15)), and a row address results in the activation of one of the 512 word lines within the selected bank.
The reduced page size RAM 500 differs from that of FIG. 1, in that an extra level of decoding is utilized to activate the sense amplifiers of two array blocks from within the selected bank, instead of all four array blocks of the bank. The extra level of decoding is accomplished by another row address bit, RA9. The value of RA9 row address bit dictates which array blocks are activated. For example, as set forth in FIG. 5, when the RA9 bit is low, array blocks are selected from quadrants 506a and 506c. When the RA9 bit is high, array blocks from quadrants 506b and 506d are selected. In FIG. 5, two array blocks (502(0.0) and 502(0,2)) are emphasized by hatching to illustrate this principle. In this case, the bank select information results in the selection of bank 504(0), and the row address results in the selection of word lines and the activation of the sense amplifier banks within array blocks (502(0,0) and 502(0,2)). In this manner, 4k sense amplifiers are enabled in a read operation in the reduced page size RAM 500, in contrast to the 8k sense amplifiers in the case of the RAM 100 of FIG. 1.
A drawback to the reduced page size RAM 500 arises out the desire to maintain a 128 bit I/O space for such a device. It will be recalled that the I/O arrangement of the RAM 100 provided 32 GIO pairs for each quadrant. Because an array bank is activated in all four quadrants in any given read operation, the RAM of FIG. 1 provides access to 128 data locations. In contrast, in the reduced page size RAM 500 array banks in only two of the four quadrants are activated in any given read operation. Thus, the same I/O arrangement of FIG. 3 (i.e., 32 bits per array bank) will not suffice for the reduced page size RAM 500, as only 64 data locations could be accessed. Thus, the I/O arrangement of the RAM 500 of FIG. 5 is modified over that of FIG. 3, to provide 64 GIO pairs for each quadrant, and thereby maintain a 128-bit I/O space.
FIG. 6 illustrates the modified I/O arrangement which provide 64 GIO pairs for each quadrant (506a-506d) in the reduced page size RAM 500. FIG. 6 sets forth the I/O line arrangement for array blocks (502(0,0) and 502(1,0)). The modified I/O arrangement has the same general configuration as that set forth in FIG. 3. Essentially one eighth of memory quadrant 506a is shown, with the array blocks (502(0,0) and 502(1,0)) being logically divided into eight array sections (600(0,0) to 600(1,7)). Each array section (600(0,0) to 600(1,7)) includes 256 bit line pairs, coupled to 128 sense amplifiers of a top sense amplifier bank, and 128 sense amplifiers of a bottom sense amplifier bank. In addition, each array section (600(0,0) to 600(1,7)) also includes a portion of a top Y-select circuit and a portion of a bottom Y-select circuit.
The I/O line arrangement of the reduced page size RAM 500 differs from that set forth in FIG. 3, in that four top LIO pairs (602(0,0) to 602(0,7)) and four bottom LIO pairs (604(0,0) to 604(1,7)) (as opposed to two top and bottom LIO line pairs) are associated with each array section (600(0,0) to 600(1,7)). The bottom LIO line pairs for one array section serve as the top LIO line pairs for the array section below. The groups of four LIO line pairs are coupled to groups of four global I/O line pairs (GIO) by top I/O select blocks (606(0,0) to 606(1,7)), and bottom I/O select blocks (608(0,0) to 608(1,7)).
It follows that in case of I/O arrangement of FIG. 6, each array section (500(0,0) to 500(1,7)) receives 64 Y-select lines. But in contrast to the large page size I/O arrangement of FIG. 3, in the reduced page size I/O arrangement of FIG. 6, an active Y-select line selects eight data bits instead of four.
The drawback to the reduced page size I/O arrangement of FIG. 6 is that it results in an increased die size. The four LIO line pairs must be repeated in each bank (504(0) to 504(15)), which can increase the size of the RAM 500 in the word line direction. In the same fashion, the four GIO line pairs must be repeated within each array bank (502(0,0) to 502(15,3)), which can increase the size of the RAM 500 in the bit line direction.
It would be desirable to provide a reduced page size RAM that does not suffer from the increased die size penalty required for increasing the number of I/O lines over larger page size RAMs.